PLDs are a well-known type of integrated circuit that may be programmed to perform specified logic functions. One type of PLD, the Field Programmable Gate Array (FPGA), typically includes an array of programmable tiles. These programmable tiles can include, for example, Input/Output Blocks (IOBs), Configurable Logic Blocks (CLBs), dedicated Random Access Memory Blocks (BRAM), multipliers, Digital Signal Processing blocks (DSPs), processors, clock managers, Delay Lock Loops (DLLs), Multi-Gigabit Transceivers (MGTs), and so forth.
Each programmable tile typically includes both programmable interconnect and programmable logic. The programmable interconnect typically includes a large number of interconnect lines of varying lengths interconnected by Programmable Interconnect Points (PIPs). The programmable logic implements the logic of a user design using programmable elements that may include, for example, function generators, registers, arithmetic logic, and so forth.
The programmable interconnect and the programmable logic are typically programmed by loading a stream of configuration data into internal configuration memory cells that define how the programmable elements are configured. The configuration data may be read from memory (e.g., from an external PROM) or written into the FPGA by an external device. The data bits can be stored in volatile memory (e.g., static memory cells), in non-volatile memory (e.g., FLASH memory), or in any other type of memory cell. The collective states of the individual memory cells then determine the function of the FPGA.
Some PLDs, such as the Xilinx Virtex® FPGA, can be programmed to incorporate blocks with pre-designed functionalities, i.e., “cores”. A core can include a predetermined set of configuration bits that program the FPGA to perform one or more functions. Alternatively, a core can include source code or schematics that describe the logic and connectivity of a design. Typical cores can provide, but are not limited to, DSP functions, memories, storage elements, and math functions. Some cores include a floor planned layout targeted to a specific family of FPGAs. Cores can also be parameterizable, i.e., allowing the user to enter parameters to activate or change certain core functionality.
In many communication applications, for example, PLDs may be used to balance the efficiency of Application Specific Integrated Circuits (ASICs) with the flexibility of software. In such systems, the PLD off-loads the Central Processing Unit (CPU) for specific algorithms that are not efficiently handled within the CPU. Such algorithms may include serial communication protocols that may operate in conformance with the communication layers within the Open System Interconnection (OSI) definition, for example.
A PLD may also be called upon to interface to the particular physical layer that is associated with the communication protocol. Thus, two main blocks of functionality may be required to interface the PLD to the particular serial communication system. First, the physical capabilities of the PLD may need to match the physical layer attributes of the communication system, such as data rate, voltage swing, encoding, etc. Second, the PLD may need to be programmed to operate in accordance with the particular communication protocol in use, such as Synchronous Optical Network/Synchronous Digital Hierarchy (SONET/SDH) or Gigabit Ethernet as specified by IEEE 802.3.
Simultaneously configuring the MGTs, processors, and the programmable logic resources to meet the requirements of all of the communication layers, however, has not yet been combined to create dynamic port provisioning.